The present invention relates to semiconductor devices, and more particularly to the structure of silicon carbide semiconductor devices which include vertical field effect transistors.
Silicon carbide (SiC) has a breakdown electric field approximately ten times larger than silicon (Si), so that when it is used for vertical field effect transistors, a drift layer (epitaxial layer) for maintaining the breakdown can be made thin and highly dense to reduce a loss. SiC-based power semiconductor devices include a junction FET (JFET) and a static induction transistor (SIT).
JP-A-9-508492 (FIGS. 6 to 11), Materials Science Forum Vols. 433–436 (2003), pp. 777–780, and IEEE ELECTRON DEVICE LETTERS VOL. 24, NO. 7, JULY 2003, pp. 463–465 disclose semiconductor devices which utilize advantages of silicon carbide (SiC). In these documents, an n+ substrate which defines a drain region, and an n− epi-layer are formed from one surface side of a silicon carbide semiconductor substrate, while an n+ source region is formed on an n-type epi-layer. Here, deep trench grooves are dug into an n-type epi-layer, and a p+ gate region is formed along the grooves. This p+ gate region extends to a position at which it comes into contact with the n+ source region. Between adjacent trench grooves, a source electrode is formed on the surface of the n+ source region, which extends along the other side, through a source contact layer which is in contact with the n+ source region. This source electrode is formed across the whole length of the semiconductor substrate on the opposite surface thereof in all directions, astride not only the surface of the n+ source region but also the surface of an insulating material in the trench grooves. On the other hand, a gate contact layer is disposed on the bottom of the trench grooves for connection with the p+ gate region. These JFET and SIT are transistors which turn on and off a current with a depletion layer which extends over a channel in the p+ gate region between a pair of adjacent trench grooves. By miniaturizing the width of this channel, a so-called “normally-off” type transistor is achieved for holding an off state even when a gate voltage is zero.
Materials Science Forum Vols. 433–436 (2003) pp. 777–780 discloses that a breakdown voltage as high as 650 volts and a forward current density as high as 250 A/cm2 can be accomplished by choosing the concentration of an n-type epi-layer, which serves as a drift layer, to be 3E15/cm−3, and a gate voltage Vg equal to zero volt, with a channel width of 2.0 μm and a groove width of 2.0 μm.
On the other hand, calculations made by the present inventors have revealed that a forward current density as high as 400 A/cm2, even exceeding that possible with silicon insulated gate bipolar transistor (IGBT) can be accomplished by increasing an impurity concentration of an epi-layer to 2E16/cm−3, and choosing a groove width of 1.0 μm (channel width of 0.5 μm) and a groove depth of 1.2 μm. However, a narrower groove width causes difficulties in drawing out a wire through a side wall for connecting a gate electrode to an external pad because of possible disconnection of metal wiring. Also, while a pad electrode could be formed by an electrically conductive region which extends through a conductive region of the gate area to reach the pad, a large resistance of the gate area makes it impossible to accomplish a transistor which can perform high speed switching operations.